1. Field of the Invention
The present invention relates to an interface circuit and, more particularly, to an interface circuit that interconnects a media access controller and an optical line termination transceiver module.
2. Description of the Related Art
In a conventional passive optical network (PON), one needs to be able to connect a media access controller (MAC) to an optical line termination Transceiver Module (TM). When the MAC and the TM are provided by the same manufacturer, connectivity is rarely an issue because the components are designed to operate together.
However, little interface standardization has occurred within the industry. As a result, it is often the case that a MAC that was produced by a first manufacturer can not be connected to a TM that was produced by a second manufacturer because the two components have incompatible interfaces.
For example, during normal operation, a TM receives a series of upstream cells from a MAC. (Each upstream cell can include, for example, 53×8 or 424 bits, based on 53 octets per cell.) Each time an upstream cell is received, the TM reacquires the needed cell timing. Further, to receive upstream cells, a TM typically requires that one burst clock-data-recovery (CDR) reset pulse accompany each upstream cell, and occur at a specific time with respect to each upstream cell.
In addition, the TM typically defines the width and active state polarity of the burst CDR reset pulse. Further, the TM has set up and hold time requirements. To meet these requirements, the burst CDR reset pulse should be received by the TM at a time that allows the rising edge of a module clock signal to occur as close as possible to a best margin position within the burst CDR reset pulse. (One position within the burst CDR reset pulse provides the best margin in terms of satisfying the set up and hold times of the TM.)
For example, a TM can output two clock signals, such as a 39 MHz (38.88 MHz) module clock signal and a 156 MHz (155.52 MHz) bit clock signal, which is 4× greater than and frequency locked to the 39 MHz signal. Further, the TM can require that the active edge of the burst CDR reset pulse occur at a particular time with respect to the start of the next burst cycle.
In addition, the TM can require that the width of the burst CDR reset pulse be equal to a number of bit times, such as four bit times (four 156 MHz bit clock periods or one 39 MHz module clock period), and be active high. Thus, four rising edges of the 156 MHz bit clock signal or four phases can occur during a burst CDR reset pulse.
Further, in this example, to insure that the set up and hold times of the TM are met, the burst CDR reset pulse should be received by the TM at a time that allows the rising edge of the 39 MHz module clock signal to occur as close as possible to the center of the burst CDR reset pulse, i.e., on the third phase or third rising edge of the four 156 MHz clock periods that define the burst CDR reset pulse.
In addition, in this example, if the rising edge of the 39 MHz module clock signal occurs on another phase or rising edge (of the four 156 MHz clock periods that define the burst CDR reset pulse), the ends of the upstream cells or the beginnings of the upstream cells can be lost. When the ends of the upstream cells are lost, the data at the ends of the cells can be lost. When the beginnings of the upstream cells are lost, the preambles can be lost. When the preambles are lost, the entire upstream cells can be lost.
Therefore, to be able to interoperate with a TM, a MAC must be able to satisfy these requirements. MACs which are designed to operate with different TMs typically have a means, such as a burst CDR generation register, that controls when the burst CDR reset pulse is generated, the width of the burst CDR reset pulse, and the active state polarity of the burst CDR reset pulse.
For example, a burst CDR register can have an N-bit field (e.g., 9-bit field) that defines 1 of 512 bit locations where the active edge of the burst CDR signal occurs with respect to the start of the next burst cycle. The register can also have a K-bit field that defines the active state pulse width. For example, the K-bit field could be 3-bits wide to allow up to an 8-bit wide active state pulse.
The burst CDR register can also have a G-bit field (e.g., 1-bit field) that defines the active state polarity of the pulse. Regardless of the method of implementation, the ability to control the generation of the burst CDR reset pulse with respect to the arrival of upstream cells is assumed to be available in MAC devices that allow interoperation with different TMs.
Thus, for example, a value equal to four can be placed in the K-bit pulse width field to define a 4-bit wide active state pulse, while a value can be placed in the G-bit polarity field to represent an active high polarity. In addition, a seed value can be placed in the N-bit field which sets the burst CDR reset pulse in its “ideal” starting position. This position is determined by the TM data sheet.
The ideal starting position, however, does not always provide the ideal position. As a result, the value placed in the N-bit field can not be used to insure that the rising edge of the 39 MHz module clock signal occurs as close as possible to the center of the burst CDR reset pulse, i.e., on the third phase or third rising edge of the four 156 MHz clock periods that define the burst CDR reset pulse.
At power up, or as a result of phase shifts occurring on the 156 MHz bit clock signal, the phase relationship of the 39 MHz module clock signal with respect to the 156 MHz bit clock signal can end up in any one of four phases. In other words, when the N-bit field has the ideal starting position, the rising edge of the 39 MHz module clock signal can occur with the rising edge of any one of the four rising edges of the 156 MHz bit clock signal that define the burst CDR reset pulse width.
For example, in one case, a value of X placed in the N-bit field of the burst CDR generation register can cause the 39 MHz module clock signal to rise on the third phase or third rising edge of the four 156 MHz bit clock periods of the burst CDR reset pulse. In another case, however, the same value of X can cause the 39 MHz module clock signal to rise on one of the other three phases or rising edges of the four 156 MHz bit clock periods of the burst CDR reset pulse which, in turn, may not provide the needed set up and hold times required by the TM.
As a result, the value placed in the N-bit field can not be used to insure that the rising edge of the 39 MHz module clock signal occurs as close as possible to the center of the burst CDR reset pulse, i.e., with the third phase or third rising edge of the four 156 MHz clock periods that define the burst CDR reset pulse.
If the MAC receives both the 39 MHz module clock signal and the 156 MHz bit clock signal, then the center of the burst CDR reset pulse can be adjusted with respect to the position of the 39 MHz module clock signal. For example, once the seed value has been loaded, the phase of the burst CDR reset pulse can be measured against the 39 MHz module clock signal. After the phase has been measured, any required bit level adjustments can then be made by loading new values in the N-bit field.
Loading new values in the N-bit field adjusts the position of the leading edge of the burst CDR reset pulse which, in turn, adjusts the phase. As a result, the phase position of the rising edge of the burst CDR reset pulse can be advanced or retarded in time by changing the value held by the N-bit field of the burst CDR generation register.
However, if the MAC has a 156 MHz clock input to receive the 156 MHz bit clock signal, but has no input to receive the 39 MHz module clock signal, then the MAC lacks any way of measuring the phase of the burst CDR reset pulse against the rising edge of the 39 MHz module clock signal. If there is no way to measure the phase, then there is no way of adjusting the phase to insure that the proper timing relationship exists between the burst CDR reset pulse and the 39 MHz module clock signal. As a result, the TM and MAC can not be reliably used together.
Thus, there is a need for an approach that insures that the TM receives the burst CDR reset pulse at the proper time with respect to the 39 MHz module clock signal when the 39 MHz module clock signal is unavailable to the MAC.